1. Field of the Invention
The present invention relates to manufacture of electrical circuitry and more particularly concerns electrical contacts of improved efficiency and configuration.
2. Description of Related Art
Both flexible and rigid circuits including integrated circuits are connected to similar circuits and other components, or to testing devices, by means of various types of connecting devices. Flat, flexible printed circuit connecting cables warrant use of similarly configured connecting devices and have been developed to a point where connection between one such printed circuit cable and another circuit is made by providing a plurality of projecting metallic interconnection features ("dots") that may be pressed against either similar features or mating metallic connecting pads on the other circuit component or components. Flexible circuit terminations or connecting wafers of this type are described in U.S. Pat. No. 4,125,310 to Patrick A. Reardon, II, deceased et al U.S. Pat. No. 4,116,517 to Selvin et al, and U.S. Pat. No. 4,453,795 to Moulin. The connectors of these patents embody a substrate having traces chemically milled thereon with a plurality of metallic raised features later formed to project from the plane of the circuit connectors. Thus, when two such connectors are placed face to face with the raised features of one in registration and contact with the other, the planes of the etched electrical circuits are suitably spaced from one another because of the projection of the features. The two circuits may be physically clamped together to press the features against one another, thereby making firm and intimate electrical contact between the two circuits.
These termination arrangements are effective and reliable in operation but difficult, costly and time consuming to manufacture. Major problems in manufacture of such connectors derive from the fact that the projecting contact buttons must be fabricated separately from (either before or after) the fabrication of the circuitry itself. This creates difficult registration problems. For example, after drilling appropriate interconnection and tooling holes through a copper clad dielectric core or substrate and plating through some of the holes to interconnect circuitry on the two sides of the core, the core is placed between the circuit artwork (optical masks) positioned on either side of the core and the holes in the artwork or datum points are then manually aligned with the predrilled holes in the core. Where dozens of parts may be made on a single panel that is 12".times.18", and alignment tolerances are measured within a few microns, registration of all or even most holes in all of the parts is exceedingly difficult, time consuming and often times not possible because of changes in dimensions of the panels following some of the processing operations. After registration of the artwork, the substantially planar circuitry is chemically milled or etched on the copper surfaces (the panel may often be covered with a coating of copper on both sides for a double sided panel). The etching process involves application of photoresist, masking the resist, exposing the resist, developing the resist, then etching through the portions of the copper not protected by the resist so that upon stripping of the remaining resist, the circuit pattern of the copper conductors remains.
Where raised interconnection features are employed, it is then necessary to plate the projecting contact features on pads formed in the circuitry which has been previously etched. These features must be precisely registered with the selected pads and with the datum of the panel. However, the panels have been previously processed to form the circuit traces so that further stresses occurring in such processing effect changes in dimension (usually, but not always, shrinkage). The changing dimensions cause severe registration problems. To manufacture the projecting contact features (sometimes called "dots"), the etched circuit is coated with a resist. Again, the appropriate artwork for defining the desired hole in the resist at the dot location must be carefully registered, which is now an even more difficult task.
In some cases, the projecting interconnection features or dots may be formed first, before the remainder of the etched circuit is formed. But, in any event, the feature must be formed separately, at a different time than the time of forming the etched circuitry, and thus the registration problems are created or exacerbated.
In such circuits, where a connection must be made from circuitry on one side of the core to circuitry on the other side of the core, holes are drilled and through-hole plated, requiring still further steps and creating other registration problems that increase cost and time of manufacture.
Conventional etched circuit processes, in general, have a number of disadvantages. Dimensional precision is difficult to achieve. The use of various etching, stripping and cleaning fluids requires special handling of hazardous chemicals. Techniques for disposal of the resulting effluents are complex and expensive, and subject to strict government controls. Etched circuit processing has a relatively low yield, greatly increasing the cost of the processing, which inherently involves a large number of costly processing steps.
Regardless of the manner in which the connections are made, it is frequently necessary to impart a type of wiping or abrasive action when one circuit is actually being connected to another so as to ensure a good electrical contact. This is so because circuits pads of many different types of materials are subject to accumulation of foreign poorly conductive materials on the contact surfaces. Thus, tin, silver, aluminum and copper contact elements, among others, will experience relatively rapid oxidation, so as to form oxide layers which tend to degrade electrical contacts made at such oxidized surface.
For this reason, gold to gold contacts are employed to eliminate the oxidation problems and improve the making of electrical contacts between several circuits. The need to use expensive gold coatings on the contacts can be avoided by use of an abrasive or wiping action when the contact is made. The wiping action physically abrades the foreign surface or oxide coating at the time of making the contact.
Gold coatings are expensive and may often require an additional processing step. The need for a wiping action can increase the cost and complexity of connecting equipment. Moreover, wiping action to ensure good contact may not be available with many different types of test probes, which are used for testing integrated circuits on a wafer before the circuits are separated from one another. In the testing of such circuits, contacts of the test probe are moved so as to touch contact pads on the integrated circuit under test, and often only a pressure action is available without any type of wiping. For this reason, it frequently happens that a desired electrical connection between a test probe contact and a contact pad on the circuit under test is not adequately made, or is not made at all, thereby degrading test results.
Accordingly, it is an object of the present invention to provide for connection between electrical circuits while avoiding or minimizing above mentioned problems.